1. Field of the Invention
The present invention relates to a device for simulating circuits, a method for simulating the same, and a computer-readable recording medium in which the circuit simulation program is stored, which are preferable for judging, after a large-scaled integrated circuit (LSI) is designed, whether or not the circuit design is suitable. In particular, the invention relates to a device for simulating circuits, a method for simulating the same, and a computer-readable recording medium in which the circuit simulation programs is stored, which are able to accelerate processes with a constant coupling capacitor regarded as a ground capacitor.
2. Description of the Related Art
In recent years, an interval of wiring has been narrowed in line with further minimization and higher integration of a semiconductor device such as memories, wherein a parasitic capacitor in wiring is increased in line with narrowing of the intervals of wiring. Particularly, as the interval of wiring becomes 0.35 μm or so, crosstalk noise is increased, influence upon the delay time and consumption of power is gradually increased. FIGS. 1A and 1B exemplarily show influences due to crosstalk noise, wherein FIG. 1A is a timing chart showing signals to be transmitted, and FIG. 1B is a timing chart showing signals which are actually transmitted.
For example, as shown in FIG. 1A, in a case where a signal repeating HIGH and LOW flows in a wire A at an interval of 10 nanoseconds and a signal repeating HIGH and LOW flows in a wire B at an interval of 20 nanoseconds, when both signals rise at the same time, the rise is accelerated, as shown in FIG. 1B. Also, when the signal flowing in the wire A and that flowing in the wire B change in the reverse direction, the rise and fall are decelerated. As a result, the duty ratio is changed, wherein the device may make an erroneous operation.
Therefore, a simulation is carried out at the stage of circuit design of a semiconductor device. A simulation apparatus for a parasitic capacitor between wires is disclosed in, for example, Japanese Laid-Open Patent Application Publication No. 6-243193 (1994). FIG. 2 is a block diagram showing a circuit simulation apparatus disclosed in Japanese Laid-Open Patent Application Publication No. 6-243193.
The prior art circuit simulation apparatus is provided with a logical connection information storing means 101 for storing logical connection information of a circuit to be analyzed, a physical connection information storing means 102 for storing the physical connection information of the circuit to be analyzed, and a test pattern information storing means 103 for storing test patterns used for simulation. It is further provided with a delay analyzing means 104 for analyzing delay of signals in wires on the basis of respective information stored in the logical connection information storing means 101, physical connection information storing means 102, and test pattern information storing means 103. In addition, a delay analysis result storing means 105 is provided, which stores the analysis results by the delay analyzing means 104.
The circuit simulation apparatus is also provided with a timing information detecting means 106 for detecting changes in the timing of signals in wires disposed close to the wire to be analyzed, on the basis of the respective information stored in the delay analysis result storing means 105 and physical connection information storing means 102, and is further provided with a timing information storing means 107 for storing timing information detected by the timing information detecting means 106. And, the apparatus is further provided with a crosstalk noise analyzing means 108 for analyzing how much crosstalk noise is brought into a wire to be analyzed, on the basis of respective information stored in the timing information storing means 107, logical connection information storing means 101, and physical connection information storing means 102.
When carrying out a simulation of crosstalk noise by using the prior art circuit simulation apparatus thus constructed, all the coupling capacitors between wires are taken into consideration as they are, and it is possible to secure high accuracy if the simulation applies to a circuit consisting of 100,000 elements or so.
However, recently, although it becomes possible to list up 10,000,000 elements or so such as resistor elements and capacitor elements in a circuit on the basis of mask data within a practical time, by using a method of layout parasitic extraction (LPE), there is a problem, by which no simulation can be carried out with respect to such a number of elements by the abovementioned circuit simulation apparatus.
An RC degeneration tool, by which the number of resistors and capacitors constituting a circuit can be reduced with no change in the electrical response of the circuit, has been put to practical use, wherein if the capacitor listed up by the LPE is a ground capacitor, which is a capacitor with respect to a ground electrode, it is possible to practically reduce the total numbers of capacitors and resistors to one hundredth or so. However, if the capacitors are coupling capacitors, the total number of capacitors and resistors can be reduced to only one tenth in practical use.
Therefore, 10,000,000 resistor elements and capacitor elements can be reduced to 100,000 elements or so if the capacitor is a ground capacitor. If the capacitors are coupling capacitors, they may be reduced to only 1,000,000 elements or so. In the case of the former, it is possible to carry out a simulation within a practical time period, but in the case of the latter, it takes a remarkably long time to carry out a simulation, and this is not practical.
If a simulation is carried out where it is assumed that the coupling capacitors between all wires are fixed like a coupling capacitor, it is possible to shorten the required time, wherein the accuracy of the simulation may be decreased.